Package structure and method of manufacturing the same

ABSTRACT

A method of manufacturing a package structure is provided, including forming a first wiring layer on a carrier board, forming a plurality of first conductors on the first wiring layer, forming a first insulating layer that encapsulates the first wiring layer and the first conductors, forming a second wiring layer on the first insulating layer, forming a plurality of second conductors on the second wiring layer, forming a second insulating layer that encapsulates the second wiring layer and the second conductors, and forming at least an opening on the second insulating layer for at least one electronic component to be disposed therein. Since the first and second insulating layers are formed before the opening, there is no need of stacking or laminating a substrate that already has an opening, and the electronic component will not be laminated and make a displacement. Therefore, the package structure thus manufactured has a high yield rate. The present invention further provides the package structure.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to package structures, and, moreparticularly, to a package structure for preventing electromagneticinterferences, and a method of manufacturing the package structure.

2. Description of Related Art

With the advancement in the technology of semiconductor package,different package structures have been developed to be incorporated inthe smart phones, tablets, internet, laptops, and such semiconductordevice is formed by mounting a chip on a package substrate such that thesemiconductor chip is electrically connected thereto, and then followedby an encapsulating process to complete the formation of thesemiconductor device. In addition, a package with an embedded chip whichhas the chip embedded in a package substrate is developed so as toreduce the overall thickness of the semiconductor package. Suchsemiconductor package is gaining popularity as it has the advantages ofreduced size as well as improved electronic performance.

FIGS. 1A to 1D are cross-sectional views showing a conventional packagestructure 1. As shown in FIG. 1A, a core board 13 having an opening 130penetrating therethrough is prepared. A plurality of inner wirings 11and a copper window 110 are formed on upper and lower sides of the coreboard 13. A plurality of conductive pillars 12 are formed in the coreboard 13 are electrically connected with the inner wirings 11.

As shown in FIG. 1B, a carrier board 10 is disposed on a bottom side ofthe core board 13. Polyimide (PI) adhesive tapes secure a semiconductorchip 18 having a plurality of electrode pads 180 to be accommodated inthe opening 130. The semiconductor chip 18 is disposed on the carrierboard 10. Through the design of the copper window 110, the semiconductorchip 18 can be prevented from making contact with the inner wirings 11.

As shown in FIG. 1C, a dielectric layer is laminated on an upper side ofthe core board 13 and on the semiconductor chip 18. A dielectricmaterial fills a gap between a wall of the opening 130 and thesemiconductor chip 18. The carrier board 10 is then removed. Anotherdielectric material is laminated on the bottom side of the core board13. The two dielectric materials form a dielectric material layer 16.

As shown in FIG. 1D, two wiring layers 14 are formed on the upper andlower sides of the dielectric material layer 16, respectively. Thewiring layer 14 has conductors 15 disposed in the dielectric materiallayer 16 and electrically connected with the electrode pads 180 and theinner wirings 11.

However, in the manufacturing process of the conventional packagestructure 1, since the copper window 110 is used as a blocking layer,the inner wirings 11 have a layout area that is reduced. Besides, as theopening 130 is formed by a CO₂ laser process, the package structure 1has a high cost, and organic fiberglass of the core board 13 is likelyexposed therefrom. Therefore, the package structure 1 has a low yieldrate and poor quality.

Blind holes (that are formed where the conductors 15 are disposed) orvias (that are formed where the conductive pillars 12 are disposed) arerequired to be formed by a laser process. The blind holes and vias thusformed can be circular only, and have poor quality.

PI tapes are used to secure the semiconductor chip 18 to the carrierboard 10. The attachment and detachment of the PI tapes to and from thecarrier board 10 adversely increase the overall cost of the packagestructure 1.

Furthermore, two dielectric materials are required to be laminated toform the dielectric material layer 16. The additional lamination andcure process increase the overall cost and time required to manufacturethe package structure 1, and may lead to displacement of thesemiconductor chip 18 (or even rotation). Therefore, it is difficult toprecisely position the semiconductor chip 18 in the opening 130, and theelectrode pads 180 of the semiconductor chip 18 are inaccurately alignedwith the conductors 15. As a result, the electrical connection is poor,and the package structure 1 thus has a low yield rate.

FIGS. 1A′ to 1D′ are cross-sectional views showing a method ofmanufacturing another conventional package structure 1′.

As shown in FIG. 1A′, a first wiring layer 11′ is formed on the carrierboard 10 such as a copper coil substrate, and a passive component 18′such as a multi-layer ceramic capacitor (MLCC) is secured on the firstwiring layer 11′ via an insulating adhesive material 180.

As shown in FIG. 1B′, a first dielectric material layer 13′ having apenetrating opening 130 is formed on the carrier board 10, and a passivecomponent 18′ is received in the opening 130.

As shown in FIG. 1C′, a second dielectric material layer is laminated onthe upper side of the first dielectric material layer 13′ and on thepassive component 18′, and fills a gap between a wall of the opening 130and the passive component 18′. The first dielectric material layer 13′and the second dielectric layer to form a dielectric encapsulating layer16′ that encapsulates and secures the passive component 18′ and thefirst wiring layer 11′.

As shown in FIG. 1D′, a second wiring layer 14′ is formed on the upperside of the dielectric encapsulating layer 16′. The second wiring layer14′ has conductors 15 disposed in the dielectric encapsulating layer 16′and electrically connected with the passive component 18′. Subsequently,the carrier board 10 is removed to expose the first wiring layer 11′.

In the conventional package structure 1′, since the copper coilsubstrate is used as the carrier board 10, it is easy to causedelamination, and the package structure 1′ is damaged. A laser processis required to form blind holes (that are formed where the conductors 15are disposed). However, the laser process can form circular blind holesonly, and the blind holes have poor quality.

Furthermore, since attaching the passive component 18′ is achievedthrough non-conductive material and a dispensing method, the diameter ofdispensing adhesive is larger than 200 μm and is difficult to controlthe volume of each dispensing adhesive, it is very easy for theinsulating adhesive material 180′ to spread to other areas, causing thewirings between each of the first wiring layer 11′ to attach to theadhesive, thereby undesirably lowering the reliability.

After another two processes of making the dielectric material layer, thedielectric encapsulating layer 16′ is formed by a lamination process,however as the first dielectric material layer 13 and the seconddielectric material layer can be mistakenly placed, not only thisincreases the time and cost, because the passive component 18′ has notyet been secured in place before baking the passive component 18′, butalso the passive component 18′ may easily become displaced, causing aloss in yield.

In addition, using conductors 15 as a means to electrically connect thepassive component 18′ may increase the electrical pathway and signalloss, and the cost of using copper electrodes (MLCC) as the passivecomponent 18′ is also very high.

Therefore, there is an urgent need to solve the above-mentioneddrawbacks of the conventional technology.

SUMMARY OF THE INVENTION

In view of the foregoing drawbacks, the present invention provides apackage structure, which comprises: a first insulating layer having afirst surface and a second surface opposing the first surface; a firstwiring layer coupled to the first surface of the first insulating layer,a plurality of first conductors disposed in the first insulating layerand electrically connected with the first wiring layer, a second wiringlayer formed on the second surface of the first insulating layer andelectrically connected with the first wiring layer via the firstconductors; a plurality of second conductors disposed on the secondwiring layer, a second insulating layer formed on the second surface ofthe first insulating layer, encapsulating the second wiring layer andthe second conductors, and having at least one opening for a portion ofa surface of the second wiring layer to be exposed therefrom; and atleast one electronic component received in the opening and electricallyconnected with the second wiring layer.

The present invention further provides a method of manufacturing apackage structure, comprising: forming a first wiring layer on a carrierboard; forming a plurality of first conductors on the first wiringlayer, forming on the carrier board a first insulating layer that has afirst surface and a second surface opposing the first surface,encapsulates the first wiring layer and the first conductors, and iscoupled to the carrier board via the first surface of the firstinsulating layer, forming on the second surface of the first insulatinglayer a second wiring layer that is electrically connected with thefirst wiring layer via the first conductors; forming a plurality ofsecond conductors on the second wiring layer; forming on the secondsurface of the first insulating a second insulating layer thatencapsulates the second wiring layer and the second conductors; formingat least one opening on the second insulating layer, for a portion of asurface of the second wiring layer to be exposed therefrom; anddisposing in the opening at least one electronic component that iselectrically connected with the second wiring layer.

In summary, the package structure and method of manufacturing the sameform two layers of wirings, and form an opening on a second insulatinglayer. Therefore, the regions that are not occupied by the secondconductors are utilized effectively, and the overall size of the packagestructure is decreased. The additional second wiring layer can alsoincrease the electrical performance and signal stability.

The present invention does not use a core board, and has a reduced sizeand a high layout usage rate.

The present invention does need to stack or laminate a substrate thatalready has an opening. Therefore, the electronic component will not bepressed to make a displacement, and can be securely positioned.

BRIEF DESCRIPTION OF DRAWINGS

The present invention can be more fully understood by reading thefollowing detailed description of the preferred embodiments, withreference made to the accompanying drawings, wherein:

FIGS. 1A to 1D are cross-sectional views showing a method ofmanufacturing a conventional package structure;

FIGS. 1A′ to 1D′ are cross-sectional views showing another method ofmanufacturing a conventional package structure;

FIGS. 2A to 2G are cross-sectional views showing a method ofmanufacturing a package structure according to the present invention;wherein FIGS. 2F′ and 2F″ are different embodiments of FIG. 2F, andFIGS. 2G′ and 2G″ are different embodiments of FIG. 2G;

FIG. 3 is a cross-sectional view of a package structure of an embodimentaccording to the present invention; and

FIG. 4 is a cross-sectional view illustrating a subsequent process ofFIG. 2G.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention is described in the following with specificembodiments, so that one skilled in the pertinent art can easilyunderstand other advantages and effects of the present invention fromthe disclosure of the present invention.

It should be noted that all the drawings are not intended to limit thepresent invention. Various modification and variations can be madewithout departing from the spirit of the present invention. Further,terms, such as “upper”, “lower”, “first”, “second” and “one” etc., aremerely for illustrative purpose and should not be construed to limit thescope of the present invention.

FIGS. 2A to 2F are cross-sectional view showing a method ofmanufacturing a package structure 2 according to the present invention.

As shown in FIG. 2A, a first wiring layer 21 a is formed on a carrierboard 20 by a patterning process, and a plurality of first conductors 22are subsequently disposed on the first wiring layer 21.

In an embodiment, the carrier board 20 is a substrate, such as a copperfoil substrate or other types of boards, without any particularlimitations.

The first wiring layer 21 comprises a plurality of electrical connectionpads 210 and a plurality of conductive traces 211. In an embodiment, thefirst conductors 22 are conductive pillars such as copper pillars.

As shown in FIG. 2B, a first insulating layer 23 having a first surface23 a and a second surface 23 b opposing the first surface 23 a is formedon the carrier board 20. The first insulating layer 23 encapsulates thefirst wiring layer 21 and the first conductors 22. The first insulatinglayer 23 is attached onto the carrier board 20 via the first surface 23a of the insulating layer 23.

In an embodiment, an end surface 22 a of the first conductors 22 isexposed from the second surface 23 b of the first insulating layer 23.

A surface 21 a of the first wiring layer 21 is flush with the firstsurface 23 a of the first insulating layer 23.

In an embodiment, the first insulating layer 23 is formed by alamination or molding process.

As shown in FIG. 2C, a second wiring layer 24 is formed on the secondsurface 23 b of the first insulating layer 23. The second wiring layer24 is electrically connected with the first wiring layer 21 via thefirst conductors 22. Subsequently, a plurality of second conductors 25is disposed on the second wiring layer 24, and a second insulating layer26 is formed on the second surface 23 b of the first insulating layer23. The second insulating layer 26 encapsulates the second wiring layer24 and the second conductors 25.

In an embodiment, the second wiring layer 24 comprises a plurality ofelectrical contact pads 240 and a plurality of conductive traces 241,and the electrical contact pads 240 and the conductive traces 241 aredirectly connected with the first conductors 22.

In an embodiment, the second conductors 25 are conductive pillars suchas copper pillars, and an end surface of the second conductor 25 isexposed from the second insulating layer 26.

In an embodiment, the second insulating layer 26 is formed by alamination or molding process.

As shown in FIG. 2D, a resist layer 27 such as a photoresist layer isformed on the second insulating layer 26, and has at least one openingarea 270, for a portion of the surface of the second insulating layer 26to be exposed therefrom. Subsequently, at least one opening 260 isformed on the second insulating layer 26 of the opening area 270, for aportion of the surface of the second wiring layer 24 (i.e., electricalcontact pads 240) to be exposed therefrom.

In an embodiment, the opening 260 is formed by a grinding process suchas pumice, or a laser process, without using a conventional cuttingprocess. Therefore, the opening 260 can be reduced in size at a cornerposition (such as bottom surface, opening position).

In an embodiment, the surface 24 a of the second wiring layer 24 isflush with the bottom surface 260 a of the opening 260.

Since the electrical contact pads 240 are not recessed due to damages bylaser, cutter, or a drill, the surface integrity is well maintained.

As shown in FIG. 2E, the resist layer 27 is removed. In an embodiment,an end surface of the second conductors 25 is exposed from the secondinsulating layer 26. As a result, it is not necessary to make contactpads on the second conductors 25, such that the space among the secondconductors 25 is utilized efficiently to form the opening 260.

As shown in FIG. 2F, the carrier board 20 is removed for exposing thefirst wiring layer 21 and the first insulating layer 23, and at leastone electronic component 28 is accommodated in the opening 260electrically connected with the second wiring layer 24, without beingencapsulated within the first insulating layer 23 or the secondinsulating layer 26. The method according to the present invention doesnot use a conventional cutting method, and a distance between theelectronic component 28 and a wall of the opening 260 can be reduced.

In an embodiment, the electronic component 28 can be an activecomponent, a passive component, or a combination thereof. The activecomponent can be a semiconductor element (such as a chip), and thepassive component can be a resistor, a capacitor or an inductor. Asshown in FIG. 2F, the electronic component 28 is a passive componentsuch as a multi-layer ceramic capacitor (MLCC), which is formed by thecurrent soldering process, without using copper electrodes of highercost, so as to reduce the overall cost.

In an embodiment, the electronic component 28 is attached securely andelectrically connected with the electrical contact pads 240 via theconductive material 280 (such as soldering material or conductiveadhesive). Through limiting the size and shape of each of the electricalcontact pads 240, the adhesive can be prevented from spreading to theadjacent electrical contact pads 240.

In another embodiment, as shown in FIG. 2F′, the electronic component28′ is an active component, and a wiring can be additionally disposedamong electrical contact pads 240 corresponding to the electroniccomponent 28′.

As shown in FIG. 2F″, a plurality of electronic components 28 a and 28 bare formed on an uneven surface i.e., a step-like structure formed inthe opening 260′, so as to increase the 3D space. In an embodiment, theelectronic component 28 a is a passive component, and the electroniccomponent 28 b is an active component.

As shown in FIG. 2G, a plurality of conductive elements 29 such assolder balls are formed on the second insulating layer 26, and theconductive elements 29 are electrically connected with the secondconductors 25. Other electronic devices (not shown) can be stacked ordisposed on the electronic elements 29.

In an embodiment, more space is available through the installation ofthe conductive elements, and the electronic component 28 is preventedfrom making contact with other electronic devices.

In an embodiment, according to the depth of the opening the surface 24a′ of the second wiring layer 24′ is higher than the bottom surface 260a of the opening 260, as shown in FIG. 2G′; alternatively, the surface24 a″ of the second wiring layer 24″ is lower than the bottom surface260 a of the opening 260, as shown in the embedded wiring of FIG. 2G″.

In an embodiment, as shown in FIG. 3, the electrical contact pads 340 ofthe second wiring layer 34 are indirectly electrically connected withthe first conductors 22 via the conductive traces 341. In other words,the electrical contact pads 340 are not directly connected with thefirst conductors 22.

In a subsequent process, as shown in FIG. 4, another electroniccomponent 40 is disposed on the first surface 23 a of the firstinsulating layer 23 and electrically connected to the first wiring layer21 through a plurality of conductive elements 41 such as solder balls.

In an embodiment, the another electronic component 40 is an activecomponent, a passive components, or a combination thereof. The activecomponent can be a semiconductor element (such as a chip), and thepassive component can be a resistor, a capacitor or an inductor. Theanother electronic component 40 shown in FIG. 4 is an active component.

In an embodiment, an opening 260 can be formed among the secondconductors 25, such that the 3D space can be fully utilized. This notonly reduces the overall size (e.g., a thickness), but also increasesthe distribution area of the second wiring layer 24. Therefore, theelectrical performance is increased with more stabilized signals.

Compared to conventional use of glassfiber as the dielectric material toform the embedded structure, the present invention does not use a coreboard, and the substrate can has its size reduced. As a result, thewiring layout area is increased in such a limited space.

In addition, the substrate with the opening does not required to bestacked or laminated, and the electronic component 28 can be preventfrom being pressed and making displacement. Therefore, the electroniccomponent can be more precisely secured in position, and the yield rateis increased.

Moreover, multiple dielectric material layers are required to belaminated to form the embedded electronic components in the method ofmanufacturing a conventional circuit board such as printed circuit boardand ball grid array (BGA), hence it is easy that a mismatch will beresulted between the height of the embedded component and the thicknessof the dielectric layer. Another way of forming the embedded electroniccomponent is through forming a cavity, by mechanical molding machine orcutting method to form an opening for each cavity on the dielectricmaterial layer, which is time consuming and expensive. The presentinvention has the advantage that it only requires a general surfacemount technology (SMT) process, followed by a molding method, withoutthe need of multiple processes for forming the openings. If the opening(such as opening 260) is formed on the outer later, only one timeprocess is needed, such as using pumice, therefore the overallproduction time and cost can be greatly reduced, which is not possiblein a conventional circuit board such as printed circuit board, or BGA.

The present invention further provides a package structure 2, 3, 4,which comprises a first insulating layer 23, a first wiring layer 21, aplurality of first conductors 22, a second wiring layer 24, 34, aplurality of second conductors 25, a second insulating layer 26, and atleast one electronic component 28.

The first insulating layer 23 has a first surface 23 a and secondsurface 23 b opposing the first surface 23 a.

The first wiring layer 21 is attached to the first surface 23 a of thefirst insulating layer 23. In an embodiment, the first wiring layer 21is embedded in the first surface 23 of the first insulating layer 23 andis flush with the first surface 23 a.

In an embodiment, the first conductors 22 are conductive pillars,disposed in the first insulating layer 23, connected with the secondsurface 23 b, and electrically connected with the first wiring layer 21.

The second wiring layer 24, 34 is formed on the second surface 23 b ofthe first insulating layer 23, and electrically connected with the firstwiring layer 21 via the first conductors 22.

The second conductors 25 are conductive pillars, and disposed on thesecond wiring layer 24.

The second insulating layer 26 is formed on the second surface 23 b ofthe first insulating layer 23, encapsulates the second wiring layer 24and the second conductors 25, and has at least one opening 260 formedthereon, for a portion of the surface of the second wiring layer 24 tobe exposed therefrom.

The electronic component 28 is disposed in the opening 260 andelectrically connected with the second wiring layer 24. In anembodiment, the electronic component 28, 28′, 28 a, 28 b is an activecomponents, a passive components, or a combination thereof.

In an embodiment, the surface 24 a, 24 a′ of the second wiring layer 24,24′ is higher than or flush with the bottom surface 260 a of the opening260.

In an embodiment, the surface 24 a″ of the second wiring layer 24″ islower than the bottom surface 260 a of the opening 260.

In an embodiment, the second wiring layer 24, 34 comprises a pluralityof electrical contact pads 340, 340 and a plurality of conductive traces341, 341 that are electrically connected with the electrical contactpads 240, 340. The electrical contact pads 240, 340 are attached andelectrically connected to the electronic component 28. The electricalcontact pads 24 are connected or are not connected with the firstconductors 22, and the conductive traces 341 are connected to the firstconductors 22. In an embodiment, the opening 260′ has a step-likestructure therein.

In an embodiment, the package structure 2 further comprises a pluralityof conductive elements 29 disposed on the second insulating layer 26 andelectrically connected with the second conductors 25.

In an embodiment, the package structure 4 further comprises anotherelectronic component 40 disposed on the first surface 23 a of the firstinsulating layer 23 and electrically connected to the first wiring layer21.

The present invention has been described using exemplary preferredembodiments. However, it is to be understood that the scope of thepresent invention is not limited to the disclosed embodiments. On thecontrary, it is intended to cover various modifications and similararrangements. The scope of the claims, therefore, should be accorded thebroadest interpretation so as to encompass all such modifications andsimilar arrangements.

1.-13. (canceled)
 14. A method of manufacturing a package structure,comprising: forming a first wiring layer on a carrier board; forming aplurality of first conductors on the first wiring layer; forming on thecarrier board a first insulating layer that has a first surface and asecond surface opposing the first surface, encapsulates the first wiringlayer and the first conductors, and is coupled to the carrier board viathe first surface of the first insulating layer; forming on the secondsurface of the first insulating layer a second wiring layer that iselectrically connected with the first wiring layer via the firstconductors; disposing a plurality of second conductors on the secondwiring layer; forming on the second surface of the first insulating asecond insulating layer that encapsulates the second wiring layer andthe second conductors; forming at least one opening on the secondinsulating layer, for a portion of a surface of the second wiring layerto be exposed therefrom; and disposing in the opening at least oneelectronic component that is electrically connected with the secondwiring layer.
 15. The method of claim 14, wherein the first wiring layerhas a surface flush with the first surface of the first insulatinglayer.
 16. The method of claim 14, wherein the first conductors areconductive pillars.
 17. The method of claim 14, wherein the secondconductors are conductive pillars.
 18. The method of claim 14, whereinthe surface of the second wiring layer is higher than or flush with abottom surface of the opening.
 19. The method of claim 14, wherein thesurface of the second wiring layer is lower than or flush with a bottomsurface of the opening.
 20. The method of claim 14, wherein the secondwiring layer comprises a plurality of electrical contact pads and aplurality of conductive traces, and the electrical contact pads arecoupled to and electrically connected with the electronic component. 21.The method of claim 20, wherein the electrical contact pads areconnected with the first conductors.
 22. The method of claim 20, whereinthe electrical contact pads are not connected with the first conductors,and the conductive traces are connected with the first conductors. 23.The method of claim 14, wherein the opening is formed by a grindingprocess or a laser process.
 24. The method of claim 14, wherein theopening has a step-like structure therein.
 25. The method of claim 14,wherein the electronic component is an active component, a passivecomponent, or a combination thereof.
 26. The method of claim 14, furthercomprising disposing on the second insulating layer a plurality ofconductive elements that are electrically connected with the secondconductors.
 27. The method of claim 14, further comprising removing thecarrier board after the opening is formed.
 28. The method of claim 27,further comprising, after the carrier board is removed, disposinganother electronic component on the first surface of the firstinsulating layer and electrically connecting the another electroniccomponent to the first wiring layer.